Hardware engineering rarely forgives mistakes. Catch an architectural error after a silicon wafer enters fabrication, and the financial damage runs into millions. Catch it early, and the entire production line survives.
Bihar-based deep-tech startup Swadeza stepped directly into that high-stakes arena at the fifth edition of SEMICON India 2026, held at Yashobhoomi in New Delhi. Operating from startup pod 6 across an exhibition floor housing over 600 companies from 52 countries, founder Shweta Suman showcased FORGE, an artificial intelligence-native engineering suite built to automate the most grueling phases of microchip verification. Swadeza stood shoulder-to-shoulder with global heavyweights IBM and Tata Electronics, proving that sophisticated semiconductor architecture can emerge from Patna just as effectively as Bengaluru or Hyderabad.
Suman took an unconventional route into deep technology. She grew up and completed her schooling in Oman, moved to Jharkhand to earn an engineering degree from the Birla Institute of Technology (BIT), Mesra, and returned to Oman to build her initial professional career. Marriage eventually brought her home to Bihar. Rather than parking her technical background, she set up Swadeza.
She started wide. The company initially delivered IT consulting, software development, and digital marketing services to stabilize its baseline operations. Yet Suman kept her long-term focus locked on specialized semiconductor design tools.
The math was obvious. Semiconductor manufacturing commands massive headlines because fabrication plants demand billions in capital expenditure. But raw fabrication is useless without front-end design, rigorous testing, and exhaustive verification. Chips carry millions of interconnected transistors. Every single component must obey exact performance parameters before factories print a single mask. Design verification engineers spend weeks writing manual tests, building models, and hunting elusive timing bugs. Suman built FORGE to strip away that manual friction.
Unlike general-purpose generative models that scrape conversational text, FORGE acts as a specialized architectural engine. The system digests a microchip's technical reference manual, builds an internal structural map of the circuit architecture, and retrieves targeted data to answer engineering queries.
Swadeza designed the platform across four discrete modules targeting sequential phases of the chip lifecycle:
| Module Name | Lifecycle Focus | Current Development Status | Key Operational Milestone |
|---|---|---|---|
| DV-FORGE | Design Verification | Active / Commercial Deployment | Completed OpenTitan Earlgrey sign-off in 30 days |
| PD-FORGE | Physical Design Violation Tracing | Active Development | Traces layout errors to causative design stages |
| PS-FORGE | Post-Silicon Validation | In Development | Silicon validation automation |
DV-FORGE, the flagship module, reads technical chip manuals to automatically generate verification plans, functional coverage models, and Universal Verification Methodology (UVM) testbenches. Swadeza tested the software against OpenTitan-class open-source systems-on-chip (SoCs) with measurable speed.
Swadeza completed the full verification sign-off for the OpenTitan Earlgrey SoC in 30 days. During that run, DV-FORGE flagged seven distinct functional bugs across approximately 40 intellectual property (IP) blocks and 2,581 registers. Its downstream derivative, Darjeeling, secured full sign-off in 21 days. Swadeza confirmed the underlying model architecture operates with 80% fewer computational tokens than standard conversational AI platforms, sharply reducing server compute overhead during high-density verification sweeps.
Swadeza’s national debut arrived alongside sharp policy shifts at both state and central levels. In January 2026, the Bihar government notified its Semiconductor Policy 2026, setting out structured incentives to lure electronics design companies and capital into the state. That state-level framework meshes directly with national industrial planning. The Union Cabinet cleared the Semicon 2.0 program in July 2026, expanding central capital subsidies and infrastructure outlays across the broader domestic hardware supply chain.
Suman continues engineering the remaining modules in the FORGE pipeline. Swadeza is advancing PD-FORGE to trace layout violations directly back to their point of origin, while moving PS-FORGE and SC-FORGE through laboratory testing to complete its end-to-end silicon design stack.
| SC-FORGE |
| Standard-Cell Optimisation |
| In Development |
| Cell library power and area tuning |